DSPIC30F2010 28-PIN DIP 16-bit Digital Signal Controller

DSPIC30F2010 28-PIN DIP Microcontroller mostly consists of 16 x 16 bit working registers. Some registers as like Status Register (SR), DO and REPEAT register, Program Space Visibility Page registers (PSVPAG), Data Table Page register (TBLPAG) and Program Counter (PC) act as address, data or offset registers.

These all are memory mapped. Some of them has a shadow register with each of these registers. Actually the shadow register is used temporarily and these can move its data or contents from its host register on the occurrence of an event.

But there is a specific condition occurs that shadow register could not access directly. At working register when a byte operation is performed, at that time just the Least Significant Byte (LSB) of the specific register is affected.

In DSPIC30F2010 28-PIN DIP dsPIC DSC devices, SOFTWARE STACK POINTER or FRAME POINTER are used. W15 is software Stack Pointer (SP), which has the ability to modify automatically by processing , calls and returns.

However, W15 could be referenced through any order but in the same manner as like all other W registers. It simplifies the reading, writing and many other manipulations of the Stack Pointer.

During a Reset ,W15 is initialized to 0x0800. You may reprogram the SP (Stack Pointer) during initialization to any position within data space. W14 register has been devoted as a Stack Frame Pointer (SP) as defined by the ULNK and LNK instructions.

Features: –

Now let us discuss the features of dsPIC30F2010 separately.

High-Performance Modified RISC CPU:

• It has Modified Harvard Architecture
• 84 base directions with flexible tending to modes
• C compiler optimized instruction set of design
• 27 intersect sources
• 3 external interrupt sources
• 24-bit wide guidelines, 16-bit wide data way
• 16 x 16-bit working register cluster
• Up to 30 MIPs task:
• DC to 40 MHz outer clock input
• 4 MHz-10 MHz oscillator contribution with PLL active (4x, 8x, 16x)
• Peripheral and External interface with sources
• 8 user selectable need levels for each hinder
• 4 processor exemptions and programming traps
• Primary and Alternate interface with Vector Tables

DSPIC30F2010 28-PIN DIP DSP Engine Features: –

• Modulo and Bit-Reversed Addressing modes
• Two, 40-bit wide aggregators with discretionary saturation logic
• 17-bit x 17-bit single cycle equipment fragmentary/whole number multiplier
• Single cycle Multiply-Accumulate (MAC) task
• Dual information fetch
• 40-organize Barrel Shifter

DSPIC30F2010 28-PIN DIP Peripheral Features: –

• High current source/sink I/O pins: 25 mA/25 mA
• Optionally combine up 16-bit timers into 32-bit clock modules
• 3-wire SPI™ modules (underpins 4 Frame modes)
• I2C™ module bolsters Multi-Master/Slave mode and 7-bit/10-bit addressing
• There addressable UART modules with FIFO buffers

Motor Control PWM Module Features: –

• Complementary or Independent Output modes
• Edge and Center Aligned modes
• Multiple obligation cycle generators
• Dedicated time base with 4 modes
• Programmable yield polarity
• Dead time control for Complementary mode
• Manual yield control
• Trigger for synchronized A/D transformations

Datasheet: –

ww1.microchip.com/…n/devicedoc/70118e.pdf

Package: –

1 x DSPIC30F2010 28-PIN DIP

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